library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity ram is
  port (
    clock        : in  std_logic;
    we, oe       : in  std_logic;
    address      : in  std_logic_vector(9 downto 0);
    bidir        : inout  std_logic_vector(15 downto 0)
  );
end entity ram;

architecture a of ram is
------------------------------------------
function convert(A: std_logic_vector(9 downto 0)) return integer is

variable result: integer range 0 to 1023;
variable power : integer range 0 to 512;

begin
	mainLoop:
	power := 1;
	result := 0;
	FOR i IN 0 to 9 LOOP
	    if A(i) = '1' then
			result := result + power;
		end if;
		power := power * 2;
	END LOOP;
return result;
end convert;
------------------------------------------
   type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0);
   signal ramMemory : ram_type;
begin

  RamProc: process(clock) is

  begin
    if rising_edge(clock) then
       if we = '1' then
          ramMemory(convert(address)) <= bidir;
       elsif oe = '1' then
          bidir <= ramMemory(convert(address));
       else
          bidir <= "ZZZZZZZZZZZZZZZZ";
       end if;
    end if;
  end process RamProc;

end architecture a;
